1. Field of the Invention
The present invention relates to a strained silicon on insulator (strained SOI) structure and a method of manufacturing the same, and more particularly, to a strained SOI structure having a small parasitic capacitance and high carrier mobility and a method of manufacturing the same.
2. Description of the Related Art
A strained silicon CMOS is a CMOS device that includes a thin, strained silicon layer on a relaxed SiGe layer. The mobility of electrons and holes within the strained silicon layer is known to be much higher than with a bulk silicon layer, and devices manufactured using a MOFET having a strained silicon channel have improved device performances compared to devices manufactured using a conventional (unstrained silicon) silicon substrate. The potential performance improvement of devices increases device driving current and mutual conductance and reduces power consumption.
The formation of the strained silicon layer is the result of tensile strain occurs on silicon grown on a substrate formed of a material having a greater lattice constant than the lattice constant of the silicon. The lattice constant of germanium Ge is approximately 4.2 which is greater than the lattice constant of silicon, and the lattice constant of silicon-germanium SiGe is linear to the concentration of germanium Ge. That is, the lattice constant of SiGe that contains 50% Ge is 1.02 times greater than the lattice constant of silicon. The epitaxial growth of silicon on a SiGe substrate generates the tensile strain of a silicon layer, and the SiGe substrate underneath the silicon layer is in a non-strained or relaxed state.
A method of forming a CMOS device having a strained silicon channel on a SiGe layer formed on an insulating substrate is disclosed in U.S. Pat. No. 6,059,895.
The difficulty in implementing the advantages of the strained silicon CMOS technique is the presence of a relaxed SiGe layer underneath the strained silicon layer. The SiGe layer interacts with the strained silicon layer in the processes of thermal oxidation, forming silicide, and annealing. Therefore, the improvement of device performance and a device yield that can be achieved may be limited during manufacturing a CMOS due to the difficulty of maintaining an integrity of material. Another disadvantage is that the thickness of the SiGe layer is added to the total thickness of a MOSFET main body. The addition of a thickness to the MOSFET is especially undesirable to the SOIFET structure since the additional thickness affects adversely to the super slim SOI device in which a MOSFET structure having a very thin channel is included.